H.264, or MPEG-4 Advanced Video Coding (AVC), is one of the most important video coding standards and will be used for many applications, such as mobile TV, HD-DVD, and HDTV. Except for the existing baseline, main, and high profiles, many important extensions of H.264 are under developed, including Scalable Video Coding (SVC) and Multi-view Video Coding (MVC). Because of the high computational complexity of H.264, efficient hardware architecture design for the encoders and decoders is a challenging research topic and is the key for widespread usage in the market. The objective of this special session is to provide a platform for related researchers to present state-of-the-art hardware architecture for implementing H.264 video coding systems. We solicit high quality and original works on the hardware design of H.264 and its extensions with application specific integrated circuits, application specific instruction-set processors, and digital signal processors. Topics of interest include but are not limited to:

- VLSI architecture design for H.264 video coding standard and its extensions (baseline profile, main profile, high profile, SVC, and MVC)

- Processors or SoC platforms those are efficient for implementing H.264

- Low power hardware architecture for H.264 for mobile applications

- Cost-effective hardware architecture for H.264 for HD applications

- Hardware-oriented algorithm design for H.264